Low-energy and tunable LIF neuron using SiGe bandgap-engineered resistive switching transistor

We have proposed leaky integrate-and-fire (LIF) neuron having low-energy consumption and tunable functionality without external circuit components. Our LIF neuron has a simple configuration consisting of only three components: one bandgap-engineered resistive switching transistor (BE-RST), one capacitor, and one resistor. Here, the crucial point is that BE-RST with a silicon–germanium heterojunction possesses an amplified hysteric current switching with a low latch-up voltage due to improved hole storage capability and impact ionization coefficient. Therefore, the proposed neuron utilizing BE-RST requires an energy consumption of 0.36 pJ/spike, which is approximately six times lower than 2.08 pJ/spike of pure silicon-RST based neuron. In addition, the spiking properties can be tuned by modulating the leakage rate and threshold through gate bias, which contributes to energy-efficient sparse-activity and high learning accuracy. As a result, our proposed neuron can be a promising candidate for executing various spiking neural network applications.


Introduction
Spiking neural networks (SNNs) demonstrate significant energy efficiency by mimicking the biological nervous system that process binary spike signals in a parallel and event-driven manner [1][2][3].Spike events are typically generated based on the leaky integrate-and-fire (LIF) neuron model [4,5].It is crucial that a substantial number of LIF neurons are required to solve parallel and complex tasks such as classification and recognition.In other words, the design of compact and low-energy LIF neurons is required to realize space-and energy-efficient SNN hardware.However, many of the reported LIF neurons were not sufficient to meet these requirements.Complementary metal oxide semiconductor (CMOS)-based neuron circuits require many transistors and capacitors, which results in substantial space occupancy and energy consumption [6][7][8].To address these critical issues, partially depleted (PD) SOI-MOSFET, L-shaped gate bipolar impact ionization MOS (L-BIMOS) and double gate-junctionless field effect transistor (DG-JLFET) have been replaced the leaky-integration function by accumulating charge in the floating-body instead of a capacitor [9][10][11].However, the absence of an automatic reset function necessitates a reset circuit for periodic LIF operation and current-to-voltage signal converters are required to ensure stable compatibility with synaptic device arrays.The operation of these external circuits inevitably leads to significant energy consumption of ~ 0.3 nJ due to the additional voltage supply requirement [9,12].In another proposal, biristor, SOI-MOSFET and germanium (Ge)-MOSFET have been suggested as a single-device neuron by using the single transistor latch phenomenon [13][14][15][16].However, the drawback lies in the significant energy consumption of ~ 0.95 nJ resulting from wide spike pulses and large latch-up voltages.
Alternatively, LIF neurons based on volatile threshold switching (TS) devices can overcome these limitations due to their low energy consumption and compact circuit configuration [17][18][19][20][21].The TS device is a type of volatile memristor that exhibits hysteric-switching behavior through electronic, atomic, and thermal phenomenon [22][23][24].These TS device neurons consume less energy due to the low operating voltage range and fast switching speed of TS devices.Additionally, the hysteresis properties of the TS device enable periodic neural oscillations without the large external circuitry which consumes additional energy.However, TS devices face challenges in practical applications because their characteristics are difficult to control consistently in non-CMOS compatible large-area fabrication.Most importantly, most TS devices applied to LIF neurons have gateless structures, making it impossible to control their spiking characteristics without hardware modifications.The tunable threshold functionalities are essential at the neuron level as they can further improve learning accuracy and energy efficiency by filtering input signals within a certain range and preventing excessive firing [25][26][27].This tunable feature can also be applied to fuzzy tasks by fine-tuning the cluster's threshold, which allows the system to more accurately classify and respond to data with varying degrees of ambiguity [28][29][30].Moreover, data loss can be averted by adjusting the spiking frequency to maintain stable operation, even with wide variations in conductance of synaptic devices [15,31,32].The three terminal TS device is applied to LIF neuron for tunable function [21].However, this neuron generates very high spike voltage and has a narrow range of adjustable spiking frequency.
A resistive switching transistor (RST) is a three-terminal transistor that exhibits volatile resistive switching characteristics based on the impact ionization effect.The RST which can be compatible of CMOS fabrication has a simple nanowire structure consisting of physical N-P-N silicon (Si) layers.Additionally, the gate structure can implement a wide range of tunable spike functions.However, during spike firing, a lot of energy is consumed due to the high latch-up voltage and slow switching speed.
In this study, we propose a CMOS compatible LIF neuron using a gated silicon-germanium (SiGe) bandgap engineered RST (BE-RST) for low energy and tunable applications through TCAD calibrated simulation.Periodic neural oscillation is successfully achieved without external circuit by using the hysteresis characteristics of the BE-RST.To emphasize the advantages of our proposed neuron, the energy consumption is compared to a LIF neuron, where the pure Si-RST is used as a replacement.The LIF operation can be intentionally tuned through the modulation of the off-state resistance and latch-up voltage of the hysteresis characteristics.With these adjustable characteristics, an analysis is conducted in terms of frequency, peak-to-peak voltage and energy consumption in response to variations in gate voltage.

Structure & characteristics of LIF neuron
Figure 1a shows the 2D cross-sectional view and 3D schematic diagram of proposed BE-RST.The BE-RST features a Si nanowire-structure consisting of n + -anode-p-channel-n + -cathode layers with the p-channel exceptionally made of SiGe material.The Ge content (x in Si 1-x Ge x ) is set to 0.6 to ensure the narrow bandgap for the p-channel.The channel area (W ch 2 ) of the nanowire is designed to be 30 × 30 nm 2 to minimize defects caused by lattice mismatch between Si and SiGe, considering the critical thickness to Ge content [33].This nanowire with SiGe hetero-bandgap structure can be fabricated via a condensation technique that concentrates Ge during a high-temperature gate oxidation process [34].The anode and cathode are highly doped with D n+ of 10 20 cm −3 .Considering sufficient impact ionization effect and hysteresis margin, the doping concentration (D p ) and length (L ch ) of p-channel are 10 18 cm −3 and 100 nm, respectively.Figure 1b depicts the basic unit block of neuromorphic hardware, consisting of interconnected pre-synapses and BE-RST based LIF neuron.The pre-synapses transmit current signals proportional to its intrinsic weights (W 1 , W 2 ,…, W n ) to the LIF neuron.Our proposed LIF neuron, shown in the dotted box, consists of three functional parts similar to a biological neuron: input electrical cables (dendrites), a cell body consisting of the BE-RST, a capacitor, and a resistor (soma), along with output electrical cables (axon).In particular, the pivotal functional part of the neuron is the cell body, which integrates synaptic inputs into the membrane potential and generates spiking events when the threshold is reached [35].The capacitor (C mem = 1 pF) integrates the weighted input current signals (I in ) in the form of a membrane potential (V mem ).The C mem was set to the minimum value that prevents overflow or underflow from pre-synaptic array, taking into account the I in level [36].The BE-RST plays a role in triggering a spike when the V mem reaches the threshold potential (V th ), resembling ionic channels embedded inside the membrane of soma.The resistor (R out = 30 kΩ) in series with BE-RST divides the V mem to generate an output spike voltage (V out ). Figure 1c shows anode current (I A )-anode to cathode voltage (V AC ) hysteresis characteristics of BE-RST when the gate voltage (V G ) is 0 V.The BE-RST rapidly transitions to the on-state at the latch-up voltage (V LU ) through the positive-feedback mechanism based on the impact-ionization effect.Afterward, during reverse V AC sweeping, the BE-RST remains on-state and returns to the off-state at the latch-down voltage (V LD ).By this mechanism, the proposed circuit configuration utilizing RST device can accurately reproduce leaky integration, depolarization, and repolarization of biological neurons.Figure 1d illustrates flow-chart of LIF operation, which consists of a leaky integration step and a spike fire step.When the I in signal is input, the RST is in the off-state, so the C mem is predominantly charged, increasing V mem .This increment corresponds to excitatory post-synaptic potential resulting from synaptic integration.On the other hand, the V mem decreases slowly during the interval time (t int ) as the C mem discharges slightly through the RST.This decrease reflects to the leaky behavior of the biological neuron.When the accumulated I in causes the voltage to reach RST (V mem -V out ) to the V LU where the V mem aligns with the V th , a sharp decrease in the resistance of RST increases the V out .This increase in the V out corresponds to the depolarization.At the same time, the I in flows through the low-resistance RST in the same direction of discharging path.Then, the C mem begins to discharge without any further charging, reducing the V mem .The V out decreases proportionally to the V mem , leading to the repolarization.During this period, no further firing can occur from the input of additional I in because the low-resistance RST prevents the C mem from being charged.This time corresponds to the refractory period.When the voltage across RST reaches the V LD , the RST quickly returns to the off-state, at which point V mem matches the resting potential (V rest ).This self-reset process completes the spike generation and automatically prepares the leaky integration operation for the next spike event.Therefore, periodic neural oscillation can be implemented through the counter-clockwise hysteresis of the RST.
Figure 2 shows the periodic spike response of the V out based on the I in , and V mem over a period of 10 μs in BE-RST-based LIF neuron.The amplitude of the I in pulses is 5 μA.The t int and pulse width (t pulse ) are 1 μs and 50 ns, respectively.In the leaky-integration step, one I in pulse increases the V mem by 0.25 V while the V out remains close to 0 V.This is because the increased V mem is mostly applied to the high-resistance BE-RST rather than the R out .When the three I in pulses are integrated, V mem reaches the V th of 1.01 V, and then the V out increases sharply to 0.32 V.When the V mem decreases to the V rest of 0.26 V, the V out returns to 0 V.This series of process completes the one cycle of spike generation in 3.3 μs.In particular, our proposed neuron exhibits low spiking energy consumption due to the low V mem operating range and steep switching time induced by the heterojunction structure of BE-RST.This will be analyzed in detail through comparison with the RST of the homojunction structure in Fig. 3.

Comparison between pure Si-RST and BE-RST based LIF neuron
Figure 3 compares the periodic spike responses based on the V mem and I A of pure Si-RST and BE-RST based LIF neurons over a period of 150 μs.The pure Si-RST features a (Si-based) homogeneous bandgap structure and is otherwise identical to BE-RST.The amplitude of the I in pulses is 1 μA.The t int and t pulse are 10 μs and 200 ns, respectively.Over the preceding 200 μs duration, the periodic spiking operation is reliably iterated through the integration of I in pulses.In the pure Si-RST neuron, the V out of 0.26 V is generated when the V mem increases to V th of 2.1 V, as shown in Fig. 3a.Meanwhile, in the proposed neuron, the V out of 0.37 V is achieved when the V mem reaches to the low V th of 1.1 V, as shown in Fig. 3b.Moreover, the on-off switching time in BE-RST neuron is 0.3 μs, which is 14 times shorter compared to 4.2 μs in pure Si-RST neuron.The low V th and short on-off switching time can result in low energy consumption per spike (E spike ).The E spike of BE-RST neuron is compared to pure Si RST neuron using the following Eq.( 1).
Here, T includes the time it takes RST to remain the on-state as well as the time it takes to return completely to the off-state.The pure Si-RST neuron consumes 2.08 pJ of E spike .In contrast, the BE-RST neuron consumes 0.36 pJ of E spike , which is 5.8 times more energy efficient than the pure Si-RST neuron.
Figure 4a compares the hysteresis characteristics between the pure Si-RST and BE-RST to analyze the low E spike of BE-RST neuron in detail.The low E spike of BE-RST neuron is due to two main factors: low V th and short on-off switching (1) time.First, the low V th is determined by the low V LU .The V LU of BE-RST is 0.89 V, which is 2.1 times lower than 1.83 V of pure Si-RST.Figure 4b shows energy band of the pure Si-RST and BE-RST when the latch-up phenomenon initiates and completes, to understand the low V LU of BE-RST.At the V LU , the excess holes are sufficiently supplied by impact ionization as the positive V AC moves electrons from the cathode region into the p-channel.The excess holes accumulate in the p-channel, reducing the potential barrier.This further promotes the injection of more electrons into the p-channel and generation of electron-hole pair.As this process occurs iteratively, it activates positive feedback within the p-channel, ultimately transitioning RST to the on-state.In other words, it can be considered that the low V LU is determined by the more efficient supply and storage of excess holes in the p-channel.In the BE-RST, the narrow p-channel bandgap increases the impact ionization coefficient, leading to the effective supply of excess holes.Furthermore, the valence bandgap offset (∆E v ) suppresses the diffusion of stored excess holes, enabling efficient storage of excess holes [37][38][39].Next, the short on-off switching time is explained by the fast discharging induced through high on-current (I on ) level.Here, the short on-off switching time is described by fast discharging induced through high on-current (I on ) level.As shown in Fig. 4a, the I on level of pure-Si RST considerably decays from 3.7 μA to 11 nA during reverse V AC sweeping.In comparison, the BE-RST maintains a high I on level from 15 μA to 2 μA.The I on level is influenced by the impact ionization coefficient and hole storage capability.The crucial point here is that the BE-RST operates within a low voltage range.In the low voltage range, the hole storage capability has a greater influence on the BE-RST than the impact ionization coefficient [37].The reason is that the impact ionization coefficient is especially amplified at high voltages, while the hole storage capability can effectively reduce the potential barrier even at low voltages.Figure 4c shows the high stored hole density inside the p-channel of BE-RST compared to the pure Si-RST in the on-state.The pure-Si RST stores 2.2 × 10 17 cm −3 holes at the V LD of 0.83 V.In contrast, the BE-RST stores 5.7 × 10 18 cm −3 holes even at the lower V LD of 0.22 V.The BE-RST can keep the potential barrier smaller by efficiently storing excess holes through the valence bandgap offset described above, thus retaining large I on until it latches down.

Tunable function
Figure 5a shows the I A -V AC hysteresis characteristics according to the modulation of the V G .As the V G increases from 0.3 V to 0.6 V, the off-current increases from 22 pA to 156 nA, while the V LU decreases from 0.63 V to 0.51 V.The larger V G lowers the potential barrier, allowing more electrons that make up the off-current to enter the p-channel.The increase in injected electrons amplifies impact-ionization rate, activating the positive feedback at smaller V AC .
Figure 5b shows the periodic spike response that can be tuned by varying V G values.As the V G increases from 0.3 V to 0.5 V, the interval between spikes decreases from 9 µs to 5 µs, while the V out decreases from 0.28 V to 0.22 V.The reduced interval is attributed to the shorter integration time as V th decreases.The V out is also determined by the V th .Here, the ratio between V out and V th is constant because the on-state current level remains almost constant regardless of the V G .In other words, the V th is distributed to BE-RST and R out in a constant ratio.It is worth noting that no spike event occurs at V G = 0.6 V as the V mem fails to reach the V th of 0.51 V.This means that the amount of charge leaked due to the off-current during the t int (Q leak ) is larger than the amount charged to the C mem per t pulse (Q mem ).That is, spikes can be generated when the I in is larger than critical I in value (I in,crit ) that satisfies the condition Q mem = Q leak at the V th .Therefore, when the V G is above 0.6 V, the spike generation can be suppressed by inducing active leaky operation with high off-current.
Figure 5c shows the spiking frequency (f s ) as a function of the I in at V G = 0.4 V, 0.5 V and 0.6 V.The I in pulse has the t pulse of 10 ns and the t int of 1 μs.When the I in increases, the f s increases due to the faster charging speed.The larger V G increases the increasing rate of the f s with respect to the I in .When the larger V G is applied, the interval between spikes reduces due to the lowered V th , resulting in a significant increase in the f s .Moreover, it is noteworthy that the I in,crit shows a more rapid increase as V G increases.This is due to the significant increase in the Q leak .The Q leak becomes very large as the thermionic emission rises exponentially with the reduction of the potential barrier.This modulation of the I in,crit enables selective response to certain range of input, inducing an energy efficient sparse activity and high learning accuracy [25,27].
Figure 6 shows the effect of adjusting the V G on the E spike when the I in is 5 μA.The E spike decreases linearly from 0.25 pJ to 0.10 pJ as the V G increases from 0.3 V to 0.5 V, except for V G = 0.6 V where the I in,crit is larger than I in = 5 μA.This is mainly due to the decrease in the V LU , which determines the V th .The formula for E spike described above can be simplified to the product of the time BE-RST remains on-state, the I on level, and V th .As the V G increases, only V th decreases, while the I on level maintains nearly constant with little difference in the on-off transition time.Therefore, the E spike can be fine-tuned through predictions taking into account the tendency of V th with respect to V G .https://doi.org/10.1186/s11671-024-04079-5Research

Performance comparison with other LIF neurons
In Table 1, BE-RST LIF neuron is compared with other LIF neurons in terms of core device, input & output type, energy per spike, tunability, spiking frequency and external circuit.The CMOS circuit-based neurons are composed of numerous components for neuronal functions, resulting in low density and large energy consumption [7].To overcome these limitations, various core devices have been utilized in LIF neuron.The PD SOI-MOSFET has a wide spiking frequency range (~ 20 MHz), but consumes a lot of energy (~ 35 pJ) [9].The L-BIMOS and DG-JLFET neuron achieve low energy consumption (~ 0.18 pJ) with a very wide frequency range (~ 2.3 GHz) [10,11].The wide frequency range of the PD SOI-MOSFET, L-BIMOS and DG-JLFET neuron is due to their integration mechanism based on floating-body effect.However, significant energy can be additionally consumed in these floating-body Si neurons which require external circuit for to current signal conversion and reset operation.Single MOSFET neuron can improve the homeostasis of neural system with its tunable threshold voltage but requires large energy for spiking behavior [15].NbOx TS-device neuron and Ag/HfO 2 TS-device neuron can realize low-energy neural oscillation without external circuit but, their gate-less structure does not provide tunable functions [18,19].On the other hand, our BE-RST neuron does not require any external circuits and can achieve a sufficiently wide tunable spiking frequency range with low-energy consumption.

Conclusion
In this work, we have demonstrated a low-energy and tunable LIF operation based on the hysteresis characteristics of gated BE-RST.The BE-RST with heterojunction structure exhibits 4 times amplified I on at 2.1 times reduced V LU compared to pure Si-RST thanks to its improved impact ionization and robust hole storage capability.Due to its hysteresis characteristics, the proposed LIF neuron consumes 0.36 pJ of energy per spike, which is 5.8 times lower than 2.08 pJ/spike of the pure Si-RST neuron.Moreover, gate bias modulates the V LU and the off-current level, which controls the input response range and spiking frequency.These tunable properties at neuron level can enhance energy efficiency and learning accuracy without hardware modification.Therefore, our proposed area-and energyefficient neurons can be a promising candidate to play a key role in the SNN implementation.Our future work will focus on comprehensively evaluating the practical performance range of the proposed neuron, including assessments of manufacturing variability and device durability.Additionally, the SNN simulations will be conducted to demonstrate the benefits of the tunable threshold function.

Fig. 1
Fig. 1 BE-RST based LIF neuron a 2D cross-sectional view and 3D schematic diagram of the BE-RST, b circuit diagram of LIF neuron which similarly implemented the functions of dendrite, soma and axon in biological neuron, c I A -V AC hysteresis characteristics of the BE-RST at V G = 0 V and d flowchart of LIF operation: leaky-integration and spike generation

Fig. 2 Fig. 3
Fig. 2 Spike response in time domain when I in pulses of 5 μA are input

Fig. 4 a
Fig. 4 a I A -V AC hysteresis characteristics of the pure Si-RST and BE-RST, b energy band of the pure Si-RST and the BE-RST when the latch-up phenomenon initiates and completes and c stored hole density of the pure Si-RST and the BE-RST

Fig. 5 a
Fig. 5 a I A -V AC hysteresis characteristics at various V G , b V mem and V out in time domain at various V G and c f s according to the I in at the various V G

Fig. 6 1
Fig.6The effects of the V G on E spike